Automatic programming problem was solved, which aims to source code generating on Verilog/VHDL hardware description language, for impulse former module which depending from user input values. Autogenerated module will be use in any user designs in automated design systems (integrated development environment) Altera Quartus II / Xilinx ISE or Vivado, for generating firmware file to field programmable gate array chips from both vendors. Autogenerated source code module will be use in any user’s engineering or technical tasks, which aims to debugging and reverse engineering.
автоматическое программирование, генератор программного кода, единичный импульс, последовательность импульсов, язык описания аппаратуры, verilog, vhdl, система автоматизированного проектирования, интегрированная среда разработки, программируемая логическая интегральная схема, automatic programming, source code autogenerator, unit impulse, impulse sequence, hardware description language, verilog, vhdl, automated design system, integrated development environment, field programmable gate array
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